PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...

The aim of the project was to traverse a packet through the TCP/IP suite using VHDL based ModelSim 6.3cSE. My role in the project was to design the flow of the packet through the TCP/IP layer and to ...

(VHDL, ModelSim, Xilinx) Simulated and synthesized a processor with a clock frequency of 25 MHz. Used Tomasulo algorithm to dynamically schedule instructions and execute them in out of program order ...

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...