EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

How UVM Callbacks Simplify Assertion Validation

Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

Plug-n-play UVM Environment for Verification of Interrupts in an IP

In a System-on Chip(SoC),a general interrupt process works as follows: Interrupt is triggered by a certain system event or interrupt source. Interrupt is detected by system’s peripheral module, which ...
Semiconductor Engineering

The Future of UVM

It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...