ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of its HES-DVM™ ...

Semiconductor Engineering sat down to explore partitioning with Raymond Nijssen, vice president of system engineering at Achronix; Andy Ladd, CEO at Baum; Dave Kelf, chief marketing officer at Breker; ...

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...

With up to 21 Xilinx Virtex-5 FPGAs, the CHIPit Platinum V5 prototyping system can handle ASIC and system-on-a-chip (SoC) designs of up to 28 Mgates. The system targets users who need early hardware ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched HES-DVM Proto Cloud Edition (CE).

With the emergence of 90-nm process technology, ASIC designers get to explore uncharted levels of performance and density. However, it has also unleashed a slew of challenging design-integrity issues, ...