Semiconductor Engineering

Formal Verification Fundamentals Remain Non-Negotiable In The New Verification Revolution

This integration addresses the fundamental barriers that have historically limited formal verification adoption: complexity ...
EDN

Specifications: The hidden bargain for formal verification

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...
Semiconductor Engineering

Coverage-Directed Test Selection Method for Automatic Test Biasing During Simulation-Based Verification

New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

What’s the Deal with SoC Verification?

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...