EDN

PLL Phase Locked Loop Invention

This fellow has a Hong Kong patent on eliminating dead-time-jitter. Well, I am not a PLL expert but I am pretty sure that a good PLL with a filter that works right should not really hunt around too ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
EDN

Free phase-locked loop (PLL) analysis software

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...
Design-Reuse

True Circuits Introduces New Line of Phase-Locked Loop Hard Macros; Significantly Smaller PLL Sizes Achieved Without Sacrificing Performance

LOS ALTOS, Calif.--(BUSINESS WIRE)--June 8, 2004-- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics ...
Design-Reuse

Selecting PLLs for ASIC Applications requires tradeoffs

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...