As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...

At Alcatel-Lucent, we test chassis-level products that provide 42 board slots on a midplane, essentially a passive backplane that accepts boards on its front and rear sides. Thirty-four of those slots ...