EDN

New error comparison scheme proposed for design rule checking flows

BENGALURU, India — With design rule checking becoming hugely complex in the deep sub-micron regime, there is a large run time for physical verification tools, for the number of design rules that must ...
Semiconductor Engineering

Managing Complexity: Evolving Approaches To Design Rule Checking In Modern IC Design

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts.
Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
EDN

Thousand design rules, million-dollar masks

The high cost of mask sets for nanometer processes creates considerable pressure to detect and correct errors as early in the physical-verification process as possible. To deliver successful, ...
Electronic Design

Rule Checker Takes RTL Analysis Into The Physical Realm

At one time, the relationship between logic designers and physical implementation specialists was simpler. Front-end designers had long been accustomed to providing their ASIC vendors with a ...
Semiconductor Engineering

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via ...
Electronic Design

Metal Fill Crosses The Threshold From Manufacturing To Design

The purpose of fill synthesis is to meet foundry CMP design rules by inserting dummy shapes on the metal, via, active, and poly layers of an IC design. These CMP rules enable the foundry to maintain a ...