Electronic Design

Signoff Evolves From Design-Rule Checking To Yield Analysis

IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...
Semiconductor Engineering

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows ...
Electronic Design

Design-Rule Checker Bets The Farm On Parallelism

Promising full-chip design-rule checking (DRC) for designs of any size and at any technology node in two hours or less, Magma's Quartz DRC is a key component of the company's recently announced Cobra ...
Semiconductor Engineering

Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted ...
Nasdaq

ASE launches its Integrated Design EcosystemTM to enable silicon package design efficiencies that reduce cycle time by half

SUNNYVALE, Calif.--(BUSINESS WIRE)-- Advanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced the launch of its Integrated ...