EDN

Synopsys Releases Upgrades To DFT, ATPG Products

Synopsys Inc. today announced it has upgraded its design-for-test (DFT) and automatic test pattern generation (ATPG) products for system-on-a-chip (SOC) design flow. The upgrades to the company’s ...
EDN

Synopsys DFT tool gets core add on

SAN MATEO, Calif.—Synopsys Inc. Monday (March 3) announced it has added new features to SoCBIST, an add-on to DFT Compiler for the creation and integration of IP cores that are optimized for test ...
Electronic Design

DTF And ATPG Enhancements, Improve Compiler Performance

A series of design-for-test (DFT) and automatic pattern generation (ATPG) products leverage advanced test modeling for dramatic capacity and performance gains in Synopsys' DFT Compiler. The TetraMAX ...
Semiconductor Engineering

Hyperconvergence Of Design For Test And Physical Design

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...
Design-Reuse

Synopsys Galaxy Design Platform Enhanced With SoCBIST Solution For Core-Based Designs

ARM-Synopsys Reference Methodology Delivers SoC Test Solution for Core-based Design Flows Mountain View, Calif., March 3, 2003-Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) ...
Design-Reuse

Synopsys Introduces New Logic BIST Capability to Significantly Reduce Test Cost

SocBIST Delivers Identical Fault Coverage with 10 Times Reduction in Test Time and 400 Times Reduction in Data Volume Compared to Full Scan MOUNTAIN VIEW, Calif., September 30, 2002 - Synopsys, Inc.
Electronic Design

DFT app supports hardware emulation

Design for testability (DFT), a way to build testability into an integrated circuit (IC) at the design stage to lower testing costs and increase manufacturing yield, has been around for many years in ...