Design-Reuse

Core-assisted approach accelerates debug of FPGA DDR II interfaces

With IO rates of several hundred megahertz, FPGAs have become an excellent medium for implementation of high-speed memory controllers. Fast memory storage and retrieval often involve implementing DDR ...
EDN

Overcoming DDR-2-interface challenges

DDR (double-data-rate) memory devices do an admirable job of unclogging the memory bottleneck between external memory and ASICs, but the nature of DDR is stretching the skills of designers creating ...
Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
EDN

TriCN fields interface IP for DDR fast-cycle RAM

San Mateo, Calif. – Traditionally late to adopt leading-edge technologies, consumer electronics devices are becoming technology drivers in some areas, as their changing use of DRAM shows. The ...
Electronic Design

DDR FCRAM Boosts Performance In DDR SDRAM Designs

A modified form of synchronous DRAM technology, double-data-rate, fast-cycle random access memory (DDR FCRAM) is primarily focused at the networking market segment. Yet due to its high performance, it ...