Business Wire

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMe TM SSD and PCIe® designs using ...
EDN

Optimizing designs with co-simulation

Engineers and EDA tool providers have been in a long-term conversation on how to improve design insight and better predict system behavior prior to prototyping. Best-in-class strategies to design ...
Design-Reuse

Analog and Mixed Signal Modeling Approaches

This article provides an insight into various approaches followed for Analog and Mixed Signal (AMS) modeling and the associated challenges. The emphasis is on analyzing various approaches and finally ...
EDN

Who is the EDA leader in SystemVerilog simulation? Part 1

A couple of weeks ago, I took a pre-briefing from the folks at Mentor Graphics and Cadence Design Systems on their plans to standardize on a jointly developed common SystemVerilog verification ...