A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...

In recent years we have begun to see references to “RF” CMOS processes and to “RF” models for those processes. This article will explore what the real meanings of such “RF” designations are, and what ...

As author R. Jacob “Jake” Baker points out in the preface to this comprehensive volume, CMOS technology has dominated the fabrication of ICs for 25 years, and is likely to dominate it for another 25 ...

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...

Creating a sensor-based IoT edge device is challenging, due to the multiple design domains involved. But, creating an edge device that combines the electronics using the traditional CMOS IC flow and a ...

Advances in integrated circuit technology and fabrication have made it possible to leverage traditional CMOS fabrication processes and materials and apply them to the design of Photonic Integrated ...

THOUSAND OAKS, Calif. — Claiming to beat the performance of the best available CCD sensors, Rockwell Science Center is introducing a CMOS system-on-chip imager for high-definition television cameras.

Low power design has become a cornerstone of modern integrated circuit development, driven by energy efficiency demands and the challenges of scaling in nanometre technologies. Innovations in ...

The recent reduction in transistor size using scaling will cause sub-threshold leakage currents to become an increasingly large component of total power dissipation. In this paper, a stack transistor ...